Damage from electrostatic discharge (ESD) is a significant failure mechanism in modern integrated circuits, particularly as integrated circuit physical dimensions continue to shrink to the sub-micron range. Electrically, an ESD event occurs upon contact of one or more of the terminals of an integrated circuit terminals with a body that is statically charged to a high voltage (up to on the order of thousands of volts). This level of static charge is readily generated by the triboelectric effect and other mechanisms acting upon humans or manufacturing equipment. Upon contact, the integrated circuit discharges the charged body through its active devices and DC current paths. If the amount of charge is excessive, however, the discharge current density can damage the integrated circuit so that it is no longer functional, or so that it is more prone to later life failure. ESD damage thus is a cause of yield loss in manufacturing, and also poorer reliability in use.
It is common practice in the art to implement, into each integrated circuit, ESD protection devices connected to the external terminals of the circuit. ESD protection devices are designed to provide a current path of sufficient capacity to safely discharge the charge applied thereto by a charged body in an ESD event, but to not inhibit the functionality of the integrated circuit in normal operation. The addition of ESD protection devices necessarily add parasitic effects that degrade circuit performance; in some cases such as series resistors, the ESD protection devices directly add delay to electrical performance. Accordingly, a desirable goal for ESD protection devices is to provide a high capacity current path, which is readily triggered during an ESD event but which can never trigger during normal operation, and which presents minimal effect on circuit performance.
An example of a conventional ESD protection device for bipolar integrated circuits is described in Avery, "Using SCR's as Transient Protection Structures in Integrated Circuits", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, (IIT Research Institute, 1983), pp. 177-180. The protection device described in this paper is a vertical silicon-controlled rectifier (SCR). As is well known, SCRs are able to conduct relatively large amounts of current with relatively little resistance, particularly when triggered to operate in their "snap-back", or "negative resistance" regime.
ESD sensitivity is particularly acute in metal-oxide-semiconductor (MOS) circuits, as such circuits primarily rely on lateral surface conduction as opposed to vertical conduction to buried layers, as is the case in bipolar circuits. Furthermore, the gate dielectric of MOS transistors is generally quite sensitive to overvoltage conditions, particularly in modern circuits having ultra-thin gate dielectrics of thicknesses on the order of 10 nm or less. An example of a lateral SCR useful in MOS circuits is described in an article by Rountree, et al., "A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, (EOS/ESD Association and IIT Research Institute, 1988), pp. 201-205. As described on page 202 relative to FIG. 2, this lateral SCR includes a parasitic n-p-n transistor formed by the n-well, p-substrate and the n+ region connected to the common terminal, while the parasitic p-n-p transistor is formed by the p+ region connected to the terminal, the n-well and the p-substrate.
Another protection scheme suitable for MOS technology which incorporates the lateral SCR is described in U.S. Pat. No. 4,896,243, issued Jan. 23, 1990. In this scheme, a field plate diode, connected in parallel with the SCR, turns on first in response to an ESD event. The higher capacity, but slower firing, lateral SCR is subsequently triggered by junction breakdown, as described at column 5, lines 36 through 43 of the reference.
By way of further background, U.S. Pat. No. 4,692,781 issued Sep. 8, 1987 describes a thick field oxide transistor used as an ESD protection device in an MOS integrated circuit. This reference further describes particular layout considerations useful in the construction of such a device, especially regarding the distance between metal contact to diffusion and the edge of the diffusion.
By way of further background, U.S. Pat. No. 4,855,620 issued Aug. 8, 1989 describes an ESD protection scheme for output devices. According to this reference, thick field oxide transistors are connected in parallel with the output driver transistors, and turn on at voltages greater than the power supply voltage of the driver so that normal operation if not affected. Copending application Ser. No. 711,549, filed Jun. 4, 1991, entitled "ESD Protection Circuit", assigned to SGS-Thomson Microelectronics, Inc. and incorporated herein by this reference, discloses a lateral n-p-n bipolar transistor useful as an ESD protection device, particularly for output devices.
By way of further background, yet another ESD protection scheme according to the prior art will now be described relative to FIGS. 5a and 5b. This scheme has been used in conjunction with output terminals, including common input/output terminals, in conventional integrated circuits. As illustrated in FIG. 5a, p-type substrate 102 has several field oxide isolation structures 106 at a surface, defining several active regions 108, 110, 111 therebetween. Interlevel dielectric layer 112 overlies the structure, with metal electrodes 114 making contact to underlying active regions 108, 110, 111 therethrough. N-type wells 104 are disposed under the locations at which metallization 114 makes contact to n-type active regions 108. Also in this conventional scheme, V.sub.ss metallization 114b and n+ regions 108b, 108c are present on all four sides of the bond pad PAD.
As shown in FIG. 5b, the structure of FIG. 5a is incorporated into an n-channel push-pull output driver. N-type active region 111 of FIG. 5a is the drain of n-type pull-down transistor 115 of FIG. 5b. The structure of FIG. 5a includes a lateral bipolar transistor 113 connected to pad PAD, having n+ region 108a as the collector, substrate 102 as the base, and n+ region 108b as the emitter; as illustrated in FIG. 5a, emitter region 108b is connected to ground (V.sub.ss) by way of metal electrode 114b. In addition, a collector-base diode is presented considering n+ region 108a as the cathode and substrate 102 as the anode. A similar lateral bipolar transistor is formed in parallel with pull-up transistor 117.
In this conventional structure, p+ region 110 contacts p-type substrate 102 and, in normal operation, is driven by a charge pump to a negative voltage V.sub.bb to present a back-gate bias to the transistors in the integrated circuit (such as transistors 115, 117 of the output driver of FIG. 5b). However, since ESD events generally occur when the integrated circuit is not powered up, substrate 102 is effectively floating during an ESD event.
As noted above, bipolar conduction as an effective method of safely conducting charge during an ESD event is well known. In the scheme of FIGS. 5a and 5b, however, when a sufficiently positive voltage is applied to pad PAD so as to cause breakdown of the diode between n+ region 108a and substrate 102, the state of parasitic bipolar transistor 113 is indefinite because the base of transistor 113 (i.e., substrate 102) is floating. In some cases, where the effective base resistance of bipolar transistor 113 is small, bipolar transistor 113 may not turn on (the base-emitter voltage being insufficient to forward bias the base-emitter junction) even for damaging levels of discharge current. In addition, even though n+ regions 108b, 108c encircle the pad PAD, the base contact regions 110 does not; as such, the effective base width of the transistor is not controlled, with current crowding likely at some locations, limiting bipolar conduction (if initiated at all).
It is therefore an object of this invention to provide an ESD protection scheme which allows for a controlled base resistance to be readily implemented into the circuit, thus providing stable operation of a parasitic bipolar transistor ESD protection device.
It is a further object of this invention to provide a large base width bipolar transistor ESD protection device, thus providing large discharge capacity.
It is a further object of the present invention to provide an improved technique for controlling turn-on voltage and current for the ESD protection scheme.
It is a further object of the present invention to provide such a technique which presents minimal performance degradation in normal operation.
It is a further object of the present invention to provide such a scheme where the bipolar transistor is protected from thermal runaway.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.